The invention relates to semiconductor structures and processing, especially those which include a trench capacitor array.
A goal of the semiconductor industry is to increase the circuit density of integrated circuits (“ICs” or “chips”) by decreasing the size of individual devices and circuit elements of a chip. However, this reduction of size creates challenges for the design and fabrication of certain devices, including memory circuits. One particular problem relates to the design and fabrication of on-chip capacitors, such as those used as storage capacitors in on-chip memories. Capacitors that are provided above the surface of the semiconductor device layer, such as stacked capacitors, do not scale as well as transistors, such that they take up an increasing proportion of the area of the chip. Capacitors which are formed below the surface of the semiconductor device layer, such as trench capacitors, are being used increasingly because such capacitors can often be scaled in a better manner than stacked capacitors.
Trench capacitors are advantageously used because they allow capacitance to be increased without necessarily requiring an increase in the amount of surface area occupied by the memory cell. The capacitance of a trench capacitor can be increased by making the trench longer, i.e. deeper, or by widening a part of the trench that lies below the device region of the substrate, such process known as “bottling.” The trench is typically filled with doped polysilicon, most commonly an n+ doped polysilicon, which serves as one plate of the capacitor, for example as a storage node, of a memory cell of a dynamic random access memory (DRAM). The second plate of the capacitor, referred to as a buried plate, is formed, for example, by outdiffusion of n+ dopants from a dopant source into a region of the substrate surrounding the lower portion of the trench. A dielectric layer separates the two plates of the capacitor.
FIG. 1 is a cross-sectional view illustrating a conventional trench capacitor array such as found in a DRAM. An array of trench capacitors 100 includes trench capacitors 110 formed in a substrate 101. Typically, the substrate is lightly doped with a p-type dopant. Each trench capacitor 110 includes a node dielectric and an n-type storage node 120, functioning as a storage electrode disposed in the trench. A buried plate region 130 is disposed in the substrate outside each trench and is doped with an n-type dopant, the buried plate thus surrounding the lower portions of the trenches.
One or more n-wells 170 are disposed at the periphery of the capacitor array 100, and may be provided as a ring structure surrounding the array 100. An n-band, shown at 160, connects the buried plate region 130 in the array to the n-wells. The purpose of the n-band is to maintain the buried plate of the array of trench capacitors at a uniform voltage, and to provide an electrical connection between the n-type buried plate region 130 and the n-type n-well 170. Contact to the n-band is made through the n-well, which extends downwardly from the surface to the buried n-band, permitting the n-band to be electrically biased.
Accordingly, it would be desirable to simplify the existing structure for contacting the buried plate and the method required to fabricate it.